Data elements that are processed by a data processor are often stored in storage elements comprising feedback loops, the storage elements being arranged in an array.
FIG. 1 shows an array 10 of memory bit cells according to the prior art. The memory bit cells are formed from back to back inverters, and this is shown in both transistor and gate form. The conventional bit cell has a line of symmetry 20 in its feedback loop and is in fact designed to be as symmetrical as possible. Generally, during the design of these devices one side, side a, is designed and this is then turned over to form side b. Thus, the design of the two sides are in effect mirror images of each other and are identical. Clearly when the cells themselves are built then they will not be exactly identical due to manufacturing tolerances.
When these devices are powered up, due to slight variations in capacitance or other properties of the two sides either a one or a zero may be stored. Thus, in an array of these devices there will be a random number of ones and zeros stored following power up.
The symmetry of storage elements with feedback loops is desirable in many respects as it results in storage elements that are perfectly balanced and that therefore have essentially the same performance whether a one or a zero is stored. If they are asymmetrical they will preferentially hold a certain value and thus, to store the other value will require more power. Thus, there is a technical prejudice in the field to make such storage elements symmetrical.
However, there are situations such as following power up, where the memory array may be accessed in consecutive cycles when meaningful data is not stored in it. In such a case, if randomly different values are stored, then randomly different values will be accessed and output. Outputting different values will cause any output stage to toggle and this toggling will consume power. In the case that the data output is not meaningful this power consumption is not needed.
Furthermore, in multi banked RAMs for example one bank may have valid data and the other not. During an access all banks will be read but only one will have meaningful data. The other bank|(s) will consume power by being read. If they contain uniform data this power consumption will be reduced as any output stage will not need to toggle.
It would be desirable to reduce the power consumption of an array of storage elements.